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[Communication] verilog for uart

Description: 通用异步接收器/发送器(UART)是能够编程以控制计算机到附加串行设备的接口的微芯片。详细来说,它提供给计算机RS-...还有高级的UART提供了一定数量的数据缓冲,这样计算机和串行设备数据流就可以保持同样的速度。-universal asynchronous receiver/transmitter (UART) can be programmed to control computer attached to the serial device interface microchips. Details, provide it to the computer RS-High ... UART also provide a certain number of data buffer, computer equipment and serial data stream can maintain the same speed.
Platform: | Size: 9216 | Author: 李志 | Hits:

[VHDL-FPGA-Verilog] 8251Verilog

Description: 通用串行异步收发器8251的Verilog HDL源代码,经过仿真验证。 -Universal Serial Asynchronous Receiver Transmitter 8251 the Verilog HDL source code, through simulation.
Platform: | Size: 15360 | Author: 钟兵 | Hits:

[VHDL-FPGA-Verilog] usart_verilog

Description: 通用串行异步收发器8251的Verilog HDL源代码.doc-Universal Serial Asynchronous Receiver Transmitter 8251 the Verilog HDL source code. Doc
Platform: | Size: 15360 | Author: 赵国柱 | Hits:

[VHDL-FPGA-Verilog] ethernet_tri_mode_rtl.tar

Description: verilog实现的异步UART代码，包括发送模块、接收模块，波特率可配置，另附PC机的c代码-Verilog realize asynchronous UART code, including the transmission module, receiver module, the baud rate can be configured, an additional PC-c code
Platform: | Size: 38912 | Author: | Hits:

[VHDL-FPGA-Verilog] Viterbi_RAKE

Description: 这是一篇介绍用verilog语言实现viterbi译码和rake接收机的文章，实用性很强的，在这里也感谢这篇文章的作着-This is a description language with verilog viterbi decoding and rake receiver of the article, very practical, here are grateful for this article was
Platform: | Size: 8838144 | Author: 骆军 | Hits:

[Software Engineering] FPGA_based_infrared_receiver_module

Description: 基于FPGA的红外接收模块，内含代码，采用VERILOG编写。-FPGA-based infrared receiver module, containing the code prepared by the use of Verilog.
Platform: | Size: 125952 | Author: 易成 | Hits:

[Industry research] UART_DESIGN

Description: The use of hardware description languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level description not only increases design productivity, but also provides unique advantages for design verification. The most dominant HDLs today are Verilog and VHDL. This application note illustrates the use of Verilog in the design and verification of a digital UART (Universal Asynchronous Receiver & Transmitter).
Platform: | Size: 141312 | Author: ltrko9kd | Hits:

[VHDL-FPGA-Verilog] Receiver

Description: UART Receiver Verilog Code
Platform: | Size: 193536 | Author: gunkaragoz | Hits:

[VHDL-FPGA-Verilog] ca

Description: 基于vhdl/verilog的gps接收机伪随机码产生程序。已经过仿真综合。-Based on vhdl/verilog of the gps receiver pseudo-random code generation process. Simulation has been integrated.
Platform: | Size: 1024 | Author: 包鼎华 | Hits:

[Other Embeded program] Receiver

Description: 基于802.11a的OFDM基带硬件设计的verilog代码，在Xilinx ISE环境下实现-The OFDM-based 802.11a baseband hardware design of the verilog code, in the Xilinx ISE environment to achieve
Platform: | Size: 2328576 | Author: 肖夜 | Hits:

[3G develop] Channel_Equalizer

Description: 802.11a接收机的信道均衡源码，verilog语言的-802.11a receiver channel equalizer source, verilog language
Platform: | Size: 226304 | Author: zhaohaishun | Hits:

[3G develop] Sampling_Frequency_Synchronization

Description: 802.11a接收机的采样频率同步源码，verilog语言的-802.11a receiver sampling frequency synchronization source, verilog language
Platform: | Size: 448512 | Author: zhaohaishun | Hits:

[Post-TeleCom sofeware systems] qpsk_relate

Description: QPSK相关接收机及匹配接收机的verilog实现-QPSK correlation receiver and matching receiver verilog implementation
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] UART

Description: the uart transmitter and receiver are used to design the data transmission for 8bit sipo and piso in verilog
Platform: | Size: 1024 | Author: prabakaran | Hits:

[VHDL-FPGA-Verilog] async_uart

Description: 用verilog写的串口接收发送通信程序，已经在cyclone EP1C12Q240C8调试通过-Serial receiver with verilog send written communication procedures, has been adopted in the cyclone EP1C12Q240C8 debugging
Platform: | Size: 2375680 | Author: 莫少宁 | Hits:

[VHDL-FPGA-Verilog] RS422_receiver

Description: UART--异步串行通讯 接收逻辑 （Verilog）16倍时钟接收-verilog--A UART Receiver 16 clock
Platform: | Size: 1024 | Author: 刘通 | Hits:

[Communication-Mobile] Receiver

Description: OFDM通信系统接收端完整verilog代码-OFDM communication system receiver complete verilog code
Platform: | Size: 1497088 | Author: 王练 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 这是一本介绍verilog语言的书籍，verilog语言应用于FPGA，可实现诸多实时处理模块，例如实时OFDM发射机和接收机的制作-verilog for FPGA，real time OFDM Transmitter and receiver
Platform: | Size: 265216 | Author: k | Hits:

[Other] serialsimulationreciever

Description: serial simulation receiver in verilog
Platform: | Size: 2048 | Author: mohsin4096 | Hits:

[VHDL-FPGA-Verilog] Receiver_spartn6_v1

Description: Implement design of UART receiver in verilog
Platform: | Size: 40960 | Author: Armaghan | Hits:
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